Spread spectrum clocks can be employed in integrated circuits (e.g., IC chips, chipsets, processors, etc.) to reduce the adverse effect of electro-magnetic interference (EMI). A spread spectrum-clocking generator (SSCG), for example, modulates the frequency of an oscillation clock signal so as to spread the bandwidth of the clock signal and lower EMI noise magnitude. For example, a serial advanced technology attachment (SATA) bus adapted for transferring data between devices may operate with high data transfer rates. At such high data rates, the generation of electro-magnetic interference can be significant. The spectral components of the electro-magnetic interference emissions can typically include peak amplitudes at the fundamental frequency of the device. The SATA standard bus with spreading technique can define a down spread to, for example, −5000 ppm, a reduced down spread to −2300 ppm or a center spread from 2300 ppm to −2300 ppm. A spread spectrum-clocking generator can thus generate a spread spectrum clocking profile that reduces the spectral amplitude of electro-magnetic interference components associated with the device.
The majority of prior art approaches for generating spread spectrum clocking involve the use of piece-wise linear emulation for generating a triangular modulation profile. FIG. 1 illustrates a graphical representation of a prior art piece-wise linear emulation of a triangular SSC profile 100. The triangular SSC profile 100 can be sub-divided into one or more regions such as regions 110, 120 and 130 with a constant ppm offset. The constant ppm offset in each region of the triangular SSC profile 100 can be emulated by a constant rate of a phase movement, as illustrated in equation (1) below:F=F0+dφ/dt  (1)
In equation (1), the parameter F0 generally represents a reference frequency from which the ppm offset can be generated. The parameter φ generally represents a phase.
FIG. 2 illustrates a block diagram of a prior art SSC generator 150. The SSC generator 150 generally includes a phase and frequency detector (PFD) 155, a charge pump (CP) 160, a loop filter (LPF) 165, a voltage controlled oscillator (VCO) 170, a phase manipulation unit 180, and a feedback divider (FBD) 175. In the configuration depicted in FIG. 2, reference clock (REFCLK) can be employed as a ‘0’ ppm offset clock in the phase and frequency detector 155 to create a ppm offset with respect to this clock. The phase and frequency detector 155 compares the reference clock with a feedback clock from the feedback divider 175 in order to align the frequency and phase of both the reference clock and the feedback clock. The output of phase and frequency detector 155 controls the charge pump 160. The output of the charge pump 160 may be low pass filtered by the loop filter 165 in order to control the voltage-controlled oscillator 170.
In the absence of a phase manipulation unit 180, the output of the voltage control oscillator 170 can be divided down in the feedback divider 175 to return to the phase and frequency detector 155. Hence, the circuit creates a bit clock in the voltage control oscillator 170 which may be higher in frequency than the reference clock by the divisor coefficient of the feedback divider 175. Such a frequency can be related to the bit rate or unit interval (UI) of a serial data transmitter. When the phase manipulation unit 180 is activated, input to the feedback divider 175 can be delayed in the phase by the value changing in time.
As the phase and frequency detector 155 tends to maintain and align frequency and phase of the reference clock and the feedback clock, the output of voltage control oscillator 170 is “pushed back” by the same amount of phase delay moving the phase of SSC in time. Hence, if the rate of a phase movement is constant in time, it may correspond to the constant ppm frequency offset of SSC in respect to the reference clock. The direction of phase movement can influence the sign of ppm offset. For example, if phase delay increases with the time, it can correspond to SSC that may be higher in frequency than the reference clock.
A phase movement control unit 185 retrieves necessary data from a LUT (Look Up Table) 190 with respect to each region (e.g., such as regions 110, 120 and 130) with constant ppm offset and block 180 processes a multi tap output from the voltage control oscillator 170 in order to create a phase change in time. Such a look up table 190 can be prohibitively large as the number of constant ppm offset regions increases. The memory including the look up tables 190 requires a significant portion of the area of an integrated circuit, which can be quite expensive to implement.
Such a prior art approach requires a relatively high ppm step between the constant ppm offset regions in order to keep the number of regions under 16 or 32. Additionally, the phase movement control unit 185 must operate at the same frequency as the phase manipulation unit 180, which can be difficult to design.
Based on the foregoing, it is believed that a need exists for an improved spread spectrum clock signal generator system and method that uses a repetition number (RN). A need also exists for an improved sigma-delta modulator for noise shaping a SSC modulation profile, as described in greater detail herein.